#1: Power Supply: VDD = 1.2V
#2: VDDQ = 1.2V
#3: VPP = 2.5V
#4: VDDSPD = 2.41V to 2.75V
#5: Functionality and operations comply with the DDR4 SDRAM datasheet
#6: 16 internal banks
#7: Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) forthe banks in the same or different bank group accesses are available
#8: Data transfer rates: PC4-2666, PC4-2400, PC4-2133, PC4-1866, PC4-1600
#9: Bi-Directional Differential Data Strobe
#10: 8 bit pre-fetch
#11: Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
#12: Supports ECC error correction and detection
#13: On-Die Termination (ODT)
#14: Temperature sensor with integrated SPD
#15: This product is in compliance with the RoHS directive.
#16: Per DRAM Addressability is supported
#17: Internal Vref DQ level generation is available
#18: Write CRC is supported at all speed grades
#19: CA parity (Command/Address Parity) mode is supported
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