#1: JEDEC standard 1.35V and 1.5V Power Supply
#2: VDDQ = 1.35V and 1.5V
#3: 800MHz fCK for 1600Mb/sec/pin
#4: 8 independent internal banks
#5: Programmable CAS latency: 11, 10, 9, 8, 7, 6, 5
#6: Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
#7: 8-bit pre-fetch
#8: Burst Length: 8 (interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write (either on the fly using A12 or MRS)
#9: Bi-directional Differential Data Strobe
#10: Internal (self) calibration: Internal self calibration through ZQ pin (RZQ: 240 ohm + 1%)
#11: On Die Termination using ODT pin
#12: Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95C
#13: Asynchronous Reset
#14: PCB : Height 1.180” (30.00mm), double sided component
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